2026

• Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs.
  David K. Oh, Hiroshi Sasaki.
  IEEE Computer Architecture Letters (CAL), 2026 (accepted for publication).
  

• Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design.
  Linfeng Zheng, Hiroshi Sasaki.
  IEEE Computer Architecture Letters (CAL), 2026 (accepted for publication).
  

• Lightweight and Tunable Soft Error Resilience for Protecting Caches and Memory against 2-Bit Errors.
  Shao-Yu Huang, Jungi Jeong, Hiroshi Sasaki, Changhee Jung.
  In Proceedings of the 47th IEEE Symposium on Real-Time Systems (RTSS), 2026 (to appear).
  

• Hardware-Accelerated Parallel Wrong-Path Execution for Spectre Gadget Detection.
  Fangzheng Lin, Zeyu Gao, Yanru Lin, Yangyu Chen, Hiroshi Sasaki.
  IEEE Computer Architecture Letters (CAL), Vol.25, Issue 1, 2026.
  

2025

• Teapot: Efficiently Uncovering Spectre Gadgets in COTS Binaries.
  Fangzheng Lin, Zhongfa Wang, Hiroshi Sasaki.
  In Proceedings of the 2025 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2025. (acceptance rate: 312/1061=29.4%)
  

2021

• RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications.
  Keisuke Nishimura, Takahiro Ishikawa, Hiroshi Sasaki, Shinpei Kato.
  In Proceedings of the 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2021. (acceptance rate: 18/42=42.9%)
  

2019

• Practical Byte-Granular Memory Blacklisting using Califorms.
  Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan.
  In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019. (acceptance rate: 80/345=23.2%)
  IEEE Micro Top Picks Honorable Mention